The present invention relates to a semiconductor device that houses semiconductor chips in a casing. More specifically, the present invention relates to a semiconductor device that facilitates electrical connection of the semiconductor chips to the outside via lead-out terminals.
The conventional semiconductor device that houses the semiconductor chips in a casing is electrically connected to the outside via lead-out terminals.
FIG. 9 is a cross sectional view of a conventional semiconductor device. Referring now to FIG. 9, a semiconductor device 90 uses a chip 94 of an insulated gate bipolar transistor (IGBT), and the chip 94 is housed in a casing formed of a metal base 91, a frame 92 and a cover 93. A substrate 95 made of ceramics, such as alumina and aluminum nitride, is mounted on the metal base 91. A pattern 95a of copper or such a conductive metal is formed on the substrate 95, and the semiconductor chip 94 is mounted on the copper pattern 95a. Patterns 95b and 95c for terminal connections are formed also on the substrate 95. The terminal connection patterns 95b and 95c are connected to the respective electrodes of the semiconductor chip 94 via respective bonding wires 95d and 95e.
A lead-out terminal 96 includes a soldering section 96a soldered to the pattern 95b, and another lead-out terminal 97 includes a soldering section 97a soldered to the pattern 95c. An end section 96b of the lead-out terminal 96 is fixed to the cover 93 such that a part of the end section 96b is exposed to the outside. An end section 97b of the lead-out terminal 97 contacts the inner side wall of the frame 92 such that a part of the end section 97b is exposed outside the cover 93 or the frame 92. Alternatively, the end section 96b of the lead-out terminal 96 may be fixed to the frame 92. The end section 97b of the lead-out terminal 97 may not contact the inner side wall of the frame 92.
The semiconductor chip 94 and the lead-out terminals 96, 97 are sealed with silicone gel 98 filled inside the frame 92.
The lead-out terminals 96 and 97 are electrically conductive thin plates, and are formed as long as possible, as far as their resistance and inductance are still low sufficiently. The lead-out terminals 96 and 97 are bent perpendicularly to the major faces. Due to these structures, the lead-out terminals 96 and 97 exhibit a capability of relaxing or relieving the stress exerted in an updown or vertical direction in FIG. 9 from outside, and the stress caused by their own thermal expansion or contraction and exerted in the vertical direction in the figure.
The shapes and arrangements of the terminals in the semiconductor device 90 as shown in FIG. 9 are determined based on the preliminary structural analysis that employs computer simulation in order to prevent crack formation at the solder. However, when a module assembled based on the results of the computer simulation is subjected to heat cycle tests, cracks are formed sometimes in the solder between the soldering section 96b of the lead-out terminal 96 and the pattern 95b.
This is presumably because the structural analysis by the computer simulation is conducted only in the two dimensions, i.e. in the up-down and right-left directions in FIG. 9, and the countermeasures for stress relaxation are taken only in the plane of the figure.
In view of the foregoing, it is an object of the invention to provide a semiconductor device that prevents crack formations in the soldered portions of the lead-out terminals while maintaining the resistance and impedance of the lead-out terminals at low values.